![]() ![]() Reduce the number of multiplications, FIFOs, and/or amount of memory on the block diagram.Try the following best practices and optimization techniques within your LabVIEW FPGA code. Adjust the build settings to optimize for area ( Note: this may increase compilation times, and may result in performance trade-offs).The following are general tips that can help you compile your projects successfully if you encounter a resource limitation: You may see that estimated usages are within acceptable levels despite the errors, so it can be difficult to determine areas to focus on. These errors generally indicate that the design requires more physical resources to implement than are available on the FPGA. Overuse of FPGA resources such as LUTs and Flip Flops. If you cannot make progress, reach out to NI Support for further assistance. This error appears to be a result of extra resources needed to place and route the design.įollow the general troubleshooting steps below for resource limitation errors. Too many Slices needed to place or fit the design. ![]() Try to reduce the usage of these specific resources. Since this error is more targeted, focus on the portions of your FPGA code which use BlockRAM or multipliers. This is because these items share routing resources in the FPGA chip fabric. Overuse of BlockRAM and Multiplier resources, specifically on Xilinx Spartan-3 based FPGA devices. If you cannot make progress using those steps, reach out to NI Support for further guidance. This error is more complex, but the general troubleshooting steps below are a good place to start. Overuse of resources due to design complexity resulting in difficulty placing the design. This error is the Xilinx Vivado compiler’s typical resource limitation error. This error is the Xilinx ISE compiler’s typical resource limitation error.įollow the general troubleshooting steps below for resource limitation errors. ![]() Overuse of FPGA resources such as Slices, LUTs, BRAM, DSPs, and Multipliers. ![]()
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